Harmonic reports Aristotle proved Ibex multiplication and division properties

Harmonic reports Aristotle proved Ibex multiplication and division properties

Harmonic says it used Aristotle, connected to a coding agent through MCP, to check Ibex RISC-V multiplication and division instructions against the Sail RISC-V specification. The agent prepared a harness, and Aristotle reported proving properties about the instructions. The reported check covers Ibex’s ibex_multdiv_fast module configured with RV32M = RV32MSingleCycle. Harmonic says eight assertions compare results with the Sail model, including checks covering division by zero, signed overflow and both values of data_ind_timing. A ninth property checks that each instruction completes, so the assertions cannot pass vacuously; Harmonic says the check has no environment assumptions. Harmonic also reports proving MUL on the RV32MFast configuration. It contrasts this with existing Ibex formal verification scripts, which it says omit a functional correctness check for MUL because model checking based tools cannot do it. The post describes Aristotle’s approach as compiling SystemVerilog and SystemVerilog Assertions into Lean 4 against a handcrafted formal model of digital circuits. Escape Meridian interpretation: these results concern the specified module, configurations and properties; they do not establish correctness for every Ibex configuration or all behavior in use. What does the full verification report show about the exact properties and proof setup?

Publication: 761ef5bd-ebe6-4254-85e3-de278fb0b00a

attribution — pass: The reading consistently attributes the proof results, the comparison with existing Ibex scripts, and the description of Aristotle's method to Harmonic. The Escape Meridian interpretation is clearly labeled.

Aristotle proved 9 properties about MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM and REMU.

summary — uncertain: The reading is faithful, but a non-specialist cannot easily follow it. It never says that Ibex is a RISC-V CPU core from lowRISC. It also does not explain formal verification, MCP, Sail, SystemVerilog, Lean 4, harness, or what 'pass vacuously' means. It gives little explanation of why proving MUL matters beyond the model-checking contrast. Smallest repair: one plain sentence on what Ibex is and what formally verifying an instruction means, plus term-library tooltips for the remaining terms.

It takes one sentence to formally verify that all the multiplication and division instructions of the Ibex RISC-V CPU compute the right result.

date — pass: originalPublished (2026-11-03, publisher page) matches the feed entry and the first observation. No earlier publication is indicated.

support — uncertain: The draft says the eight assertions include checks covering division by zero, signed overflow and both data_ind_timing values. The source says only that the prompt asked Aristotle to cover these. It does not explicitly state that the proved assertions cover them. Smallest repair: say Harmonic reports the prompt asked for these cases to be covered. Other claims and the labeled interpretation are supported.

The prompt asked Aristotle to cover division by zero, signed overflow (0x80000000 / -1) and both values of data_ind_timing.

media — pass: The selected media is the verified direct link to the original Harmonic post. This is the most direct way for readers to access the source.