Zhang, Songyang, Zhang, Yuzhong, Dinavahi, Venkata · Oct 28, 2026
Physics-Guided Inferencer-in-the-Loop Digital-Twin for Real-Time Adaptive Emulation of Nonlinear PMSMs
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Songyang Zhang, Yuzhong Zhang, and Venkata Dinavahi propose an Inferencer-in-the-Loop architecture for digital twins of permanent magnet synchronous machines (PMSMs). A retrains a physics-guided network while a field-programmable gate array (FPGA) runs the last accepted weights, allowing the model to adapt without interrupting its execution. In tests involving simulated machine conditions, the authors report FPGA kernel of 0.30–0.34 μs and retraining near final loss within 94 s for a shifted machine. On a 200-W drive, they report that a residual model predicted current and torque faster than real and had lower current error than an independently fitted grey-box model across six held-out runs. During loaded heating, its online-updated heads tracked a reported winding-resistance rise. The results suggest a possible way to keep hardware-in-the-loop machine models aligned with changing machines, but the abstract reports specific tests, not evidence of performance across other machines or deployments. How well does the approach transfer to machines and operating conditions beyond those tested?
Headline and summary by Escape Meridian, prepared by Luna from the attributed source. A source check is not independent confirmation of the source’s claims.
Original source
eess.SY · Article
Source details
Original source date: Oct 28, 2026 (2026-10-28).
Date basis: Date basis not provided.
Added to Escape Meridian: 2026-11-13T20:16:07.485Z. First observed: 2026-10-30T06:42:32.590Z. Retrieved: 2026-10-30T08:17:22.487Z.
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Limits
The reported results concern the particular tests described in the abstract; it does not establish how well the approach transfers to other machines or operating conditions. The evidence provided is the paper's abstract, not its full methods or results.
Open question
How well does the approach transfer to machines and operating conditions beyond those tested?
Source-stated
The authors propose an architecture in which a GPU retrains a machine-learning network while an FPGA executes its last accepted weights.
a GPU retrains the network while a field-programmable gate array (FPGA) executes the last accepted weights.
Source-stated
For damper circuits, shifted parameters, and an FEA-calibrated saturated machine, the authors report FPGA kernel latencies of 0.30–0.34 μs and retraining near final loss within 94 s for a shifted machine.
average normalized mean absolute errors (NMAEs) of 0.19%-0.67% at measured FPGA kernel latencies of 0.30-0.34 $\mu$s, and retraining for a shifted machine nears its final loss within 94 s.
Source-stated
On a 200-W drive, the authors report that a residual model's current error on six held-out runs was lower than that of an independently fitted grey-box model.
On six held-out runs (1193 s), its $i_q$ error is 5.9%-9.4% of measured RMS, against 10.4%-13.2% for an independently fitted grey-box model
Source-stated
During loaded heating, the authors report that online-updated model heads tracked a 4.1% rise in winding resistance with an RMS error of 0.44 mΩ.
over 30 min of loaded heating its online-updated heads track a 4.1% winding-resistance rise with an RMS error of 0.44 m$\Omega$.
Source and contributor context
Zhang, Songyang, Zhang, Yuzhong, Dinavahi, Venkata · Article author
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Terms and references
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Graphics processing unit
A chip that performs many calculations at once; the main hardware used to train and run AI models.
Machine learning
Methods that let computers learn patterns from examples instead of following rules written by hand.
Latency
The delay between sending a request and receiving the result.
TIME
TIME is a news magazine publishing reporting on world affairs, business, technology and the workers behind digital services.
arXiv
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Editorial provenance
Version 1. Publication ID: 58d47765-8b5b-424a-83c6-2ddd838a11e6.
Prepared by gpt-6-luna; grounding review by gpt-6-luna.
Source check: uncertain by anthropic/claude-opus-5.5 on 2026-11-13T20:16:07.485Z. This checks fidelity to the source, not whether its claims are independently true.
Editorial selection: accept; reasons: material_development.
Observation: 96ee917e54af69240718908b963ac69069b59b0998d671ce42ebce6d3544691e. Source text hash: 65ca66712333c7d1dd4c90a892a71c8c06483bcfeec6030f6efc0b342731226b.
Revision and source-check history
Version 1 · 2026-11-13T20:16:07.485Z
Physics-Guided Inferencer-in-the-Loop Digital-Twin for Real-Time Adaptive Emulation of Nonlinear PMSMs
Songyang Zhang, Yuzhong Zhang, and Venkata Dinavahi propose an Inferencer-in-the-Loop architecture for digital twins of permanent magnet synchronous machines (PMSMs). A retrains a physics-guided network while a field-programmable gate array (FPGA) runs the last accepted weights, allowing the model to adapt without interrupting its execution. In tests involving simulated machine conditions, the authors report FPGA kernel of 0.30–0.34 μs and retraining near final loss within 94 s for a shifted machine. On a 200-W drive, they report that a residual model predicted current and torque faster than real and had lower current error than an independently fitted grey-box model across six held-out runs. During loaded heating, its online-updated heads tracked a reported winding-resistance rise. The results suggest a possible way to keep hardware-in-the-loop machine models aligned with changing machines, but the abstract reports specific tests, not evidence of performance across other machines or deployments. How well does the approach transfer to machines and operating conditions beyond those tested?
Original source
eess.SY · Article
Source details
Original source date: Oct 28, 2026 (2026-10-28).
Date basis: Date basis not provided.
Added to Escape Meridian: 2026-11-13T20:16:07.485Z. First observed: 2026-10-30T06:42:32.590Z. Retrieved: 2026-10-30T08:17:22.487Z.
Limits
The reported results concern the particular tests described in the abstract; it does not establish how well the approach transfers to other machines or operating conditions. The evidence provided is the paper's abstract, not its full methods or results.
Open question
How well does the approach transfer to machines and operating conditions beyond those tested?
Source-stated
The authors propose an architecture in which a GPU retrains a machine-learning network while an FPGA executes its last accepted weights.
a GPU retrains the network while a field-programmable gate array (FPGA) executes the last accepted weights.
Source-stated
For damper circuits, shifted parameters, and an FEA-calibrated saturated machine, the authors report FPGA kernel latencies of 0.30–0.34 μs and retraining near final loss within 94 s for a shifted machine.
average normalized mean absolute errors (NMAEs) of 0.19%-0.67% at measured FPGA kernel latencies of 0.30-0.34 $\mu$s, and retraining for a shifted machine nears its final loss within 94 s.
Source-stated
On a 200-W drive, the authors report that a residual model's current error on six held-out runs was lower than that of an independently fitted grey-box model.
On six held-out runs (1193 s), its $i_q$ error is 5.9%-9.4% of measured RMS, against 10.4%-13.2% for an independently fitted grey-box model
Source-stated
During loaded heating, the authors report that online-updated model heads tracked a 4.1% rise in winding resistance with an RMS error of 0.44 mΩ.
over 30 min of loaded heating its online-updated heads track a 4.1% winding-resistance rise with an RMS error of 0.44 m$\Omega$.
Source and contributor context
Zhang, Songyang, Zhang, Yuzhong, Dinavahi, Venkata · Article author
These are credits stated by the source; they do not establish a profile match or authorship of every passage.
Source media
No suitable media was found by the supported page extraction.
Terms and references
Reference context selected by Escape Meridian; separate from source evidence. Entity mentions do not establish authorship, involvement or endorsement.
Graphics processing unit
A chip that performs many calculations at once; the main hardware used to train and run AI models.
Machine learning
Methods that let computers learn patterns from examples instead of following rules written by hand.
Latency
The delay between sending a request and receiving the result.
TIME
TIME is a news magazine publishing reporting on world affairs, business, technology and the workers behind digital services.
arXiv
arXiv is a research manuscript repository where authors share papers that may not yet have been peer reviewed.
Editorial provenance
Version 1. Publication ID: 58d47765-8b5b-424a-83c6-2ddd838a11e6.
Prepared by gpt-6-luna; grounding review by gpt-6-luna.
Source check: uncertain by anthropic/claude-opus-5.5 on 2026-11-13T20:16:07.485Z. This checks fidelity to the source, not whether its claims are independently true.
Editorial selection: accept; reasons: material_development.
Observation: 96ee917e54af69240718908b963ac69069b59b0998d671ce42ebce6d3544691e. Source text hash: 65ca66712333c7d1dd4c90a892a71c8c06483bcfeec6030f6efc0b342731226b.
uncertain · 2026-11-13T20:16:07.485Z · anthropic/claude-opus-5.5
Publication: 58d47765-8b5b-424a-83c6-2ddd838a11e6
attribution — pass: The reading correctly credits the proposal and results to Songyang Zhang, Yuzhong Zhang and Venkata Dinavahi, and keeps the results attributed with phrasing like 'the authors report'.
Authors:Songyang Zhang, Yuzhong Zhang, Venkata Dinavahi
summary — uncertain: A non-specialist cannot readily follow the reading. It never explains that a PMSM is a type of electric motor, or why a digital twin matters. The abstract's own context is omitted: the twin lets drive controllers be tested in hardware-in-the-loop before they meet the real machine, and today its maps are regenerated offline when the machine changes. Central terms are left unexplained, including kernel latency, residual model, grey-box model, held-out runs and heads. The title is the raw jargon-heavy paper title. Smallest repair: add one plain sentence giving the motor-controller-testing purpose and the offline-regeneration problem the work addresses.
allows drive controllers to be tested in hardware-in-the-loop (HIL) before they meet the real machine
date — pass: originalPublished is 2026-10-28, which matches the arXiv v1 submission date. The feed date of 2026-10-30 is correctly not used.
[Submitted on 28 Oct 2026]
support — uncertain: The summary calls the damper-circuit, shifted-parameter and FEA-calibrated tests 'simulated machine conditions', but the abstract never says they were simulated. It also says the architecture allows the model to adapt 'without interrupting its execution', which is an unlabeled inference; the source only says the FPGA runs the last accepted weights while the GPU retrains. The listed claims and their excerpts otherwise match the source. Repair: drop 'simulated', or label it as an interpretation, and attribute or condition the no-interruption point.
For damper circuits, shifted parameters, and an FEA-calibrated saturated machine, one kernel form reaches average normalized mean absolute errors (NMAEs) of 0.19%-0.67%
media — pass: The selected media is the verified arXiv abstract page for this paper, which is the direct original source.
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A chip that performs many calculations at once; the main hardware used to train and run AI models.
Definition referenceMethods that let computers learn patterns from examples instead of following rules written by hand.
Definition referenceThe delay between sending a request and receiving the result.
Definition referenceTIME is a news magazine publishing reporting on world affairs, business, technology and the workers behind digital services.
Explore TIMEarXiv is a research manuscript repository where authors share papers that may not yet have been peer reviewed.
Explore arXivA chip that performs many calculations at once; the main hardware used to train and run AI models.
Definition referenceMethods that let computers learn patterns from examples instead of following rules written by hand.
Definition referenceThe delay between sending a request and receiving the result.
Definition referenceTIME is a news magazine publishing reporting on world affairs, business, technology and the workers behind digital services.
Explore TIMEarXiv is a research manuscript repository where authors share papers that may not yet have been peer reviewed.
Explore arXiv